The present invention relates to semiconductor devices, and more particularly, to semiconductor devices having a channel region and a method of manufacturing the same.
As the integration density of semiconductor (integrated circuit) devices increases, the distance between respective devices fabricated on a substrate of a semiconductor device decreases. As a result, it has become more difficult to prevent adjacent semiconductor devices from interfering with one another using conventional isolation methods, such as local oxidation of silicon (LOCOS) or trench isolation. Ion implantation to limit or prevent punch-through at a lower portion of an isolation layer has been proposed to address a latch-up phenomenon where adjacent semiconductor devices affect one another when operating. This type of ion implantation, however, may not be an efficient approach to provide isolation where the distance between semiconductor devices is decreased beyond the point where this type of ion implantation is effective due to the increase of the integration density of the semiconductor devices.
A silicon-on-insulator (SOI) wafer approach, which may isolate semiconductor devices from one another more efficiently than the above ion implantation technique, has been developed. An SOI wafer is typically composed of a silicon wafer, and an insulation layer and a silicon layer formed on the silicon wafer. An active layer, on which semiconductor devices are formed, is an uppermost silicon layer of such an SOI structure.
FIGS. 1 through 4 are cross-sectional views illustrating a conventional method of manufacturing an SOI wafer. Referring to FIGS. 1 and 2, a base wafer A and a bonding wafer B are prepared. The base wafer A includes a silicon wafer 10 and an oxide layer 11 formed on the silicon wafer 10. The bonding wafer B includes a silicon wafer 20, an isolation layer 21 deposited on the silicon wafer 20, and a silicon layer 22 formed on the isolation layer 21. The isolation layer 21 may be formed of a variety of materials. For example, the isolation layer 21 may be a porous silicon layer or an ion-implanted silicon layer.
As shown in FIG. 3, the bonding wafer B is placed on the base wafer A such that the silicon layer 22 of the bonding wafer B contacts the oxide layer 11 of the base wafer A, and then the resulting wafer structure is heat-treated so that the bonding wafer B is bonded to the base wafer A. As shown in FIG. 4, the isolation layer 21 is removed from the wafer structure of FIG. 3 so that the silicon wafer 20 of the bonding wafer B is separated from the base wafer A. Thereafter, the silicon layer 22 of the bonding wafer B is planarized.
As described above, an SOI structure composed of the silicon wafer 10, the oxide layer 11, and the silicon layer 22 may be formed. The silicon layer 22 serves as an active layer on which active devices, such as MOS transistors, may be formed. Therefore, the thickness of the silicon layer 22 may affect the performance of such MOS transistors. For example, in order to limit the short channel effect of MOS transistors, the thickness of the silicon layer 22 should generally be decreased.
Depending on the purpose of usage, semiconductor devices which are usually formed on different wafers, i.e., semiconductor devices formed on a bulk silicon wafer and semiconductor devices formed on an SOI structure, may need to be formed together on a single semiconductor wafer. In other words, bulk silicon is generally used when forming devices in a peripheral region, which typically requires heat dissipation and a considerable amount of current, while an SOI structure is generally used when forming devices in a cell region, which, compared to the peripheral region, generally produces little leakage current, typically only rarely suffers from latch-up, and generally does not require as much heat dissipation. For example, an electrostatic prevention device, to which a high electric field is applied, may be formed in the peripheral region on a bulk silicon wafer, and a memory device, which stores data therein, may be formed in the cell region on an SOI structure.
In a conventional method of forming an SOI structure, however, bonding, separating, and polishing of the SOI structure should generally be performed separately from one another. In other words, an SOI structure region typically should be formed in a semiconductor wafer by using the processes illustrated in FIGS. 1 through 4, and then a bulk silicon region should be formed by removing the SOI structure region from the semiconductor wafer, which typically results in an increase in the manufacturing costs of the semiconductor devices and may make mass production of the semiconductor devices more difficult and/or expensive.